1. Field of the Invention
The present invention relates to an insulated-gate type integrated circuit and more particularly, a MOS type integrated circuit having a MOSFET which is operable with a higher supply voltage than 5 volts or required for production of a high voltage output.
2. Description of the Related Art
It is known that the structure of a MOSFET operable with a high supply voltage or required for generation of a high voltage output for use in a semiconductor integrated circuit commonly incorporates an LDD (lightly doped drain) arrangement or a GDD (graded diffused drain) arrangement.
FIG. 1 is a plan view showing the drain pattern of a conventional CMOS inverter in which a couple of MOSFETs having the LDD arrangement are provided in the N- and P-channel sides, respectively. FIG. 2 is a cross sectional view taken along the line I--I of FIG. 1, illustrating the element arrangement of the CMOS inverter.
In FIGS. 1 and 2, there are denoted by reference numerals an N-type semiconductor substrate 110, a P-well region 111, an element separation region 112, source and drain regions 113 and 114 of a P-channel MOSFET, source and drain regions 115 and 116 of an N-channel MOSFET, a gate electrode 117 (with lead line) arranged in an insulated gate layer 118 above the substrate or well region surface, and an aluminum lead line 119 arranged on an insulating layer 120 across the substrate 110.
Each of the drain regions 114 and 115 of the P- and N-channel MOSFETs is consisted of, in combination, a low concentration impurity diffused region (P- or N- region) and a high concentration impurity diffused region (P+ or N+).
When a lower potential is applied to the gate electrode 117, the N-channel MOSFET becomes turned OFF and the P-channel MOSFET becomes turned ON. Also, it is assumed that a supply voltage of a higher potential is fed to both the source region 113 of the P-channel MOSFET and the N-type substrate 110 and of a lower potential is fed to both the source region 116 of the N-channel MOSFET and the P-well region 111.
Then, as shown in FIG. 2, the aluminum lead line 119 on the drain diffused region is maintained at a high potential (which is denoted by .sym.) and equals the potential of the drain regions 114 and 115.
Accordingly, there are two PN junctions which exhibit a reverse bias state. One of the two PN junctions is between the P-well region 111 and the N-type substrate 110. In general, both the P-well region 111 and the N-type substrate 110 contain a low concentration of impurities and thus, a junction sustaining voltage between them will be as high as 70 to 100 volts.
The other PN junction between the P-well region 111 and the drain region 115 (including N+ and N- regions) of the N-channel MOSFET is associated with some drawbacks and then, illustrated in enlargement in FIG. 3
This will be described with reference to three separate areas of the PN junction: (1) between the P-well region 111 and the lowermost area of the N+ region, (2) between the P-well region 111 and a gate electrode side portion of the N-region, and (3) between the P-well region 111 and a far side portion (at a far side from the gate electrode 117) of the N-region.
The PN junction area 1) has a depletion layer developed into the low concentrated P-well region 111 and exhibits a sustaining voltage of 50 to 70 volts. The depletion layer of the PN junction area (2) is dislocated towards the N-region by the action of the electric field of the gate electrode 117 whereby electric energy will be biased in intensity. However, adjustment on the concentration of impurities in the N- region causes the depletion layer to expand toward the inside of the N-region so that an unwanted concentration of energy can be avoided. As the result, the sustaining voltage will be 40 to 50 volts. The depletion layer of the PN junction area (3) is developed due to lesser effects of the electric field of the gate electrode 117 and the sustaining voltage of the same will remain higher than that of the area 2).
As set forth above, the sustaining voltage of the drain junctions in an N-channel MOSFET can be maintained to the level of the prior art when the potential of the aluminum lead line 119 provided above the drain regions is high.
When the potential of the aluminum lead line 119 is low (equal to the low potential of the gate electrode 117, denoted by .crclbar.), the sustaining voltage between the P-well region and the N-type substrate exhibits 70 to 110 volts.
FIG. 4 is an enlarged view showing the PN junction between the P-well region 111 and the drain region (including N+ and N-regions) in the N-channel MOSFET. Similarly, while the PN junction is separated into three areas for ease of description, the area 1) between the P-well region 111 and the lowermost of the N+ region exhibits a sustaining voltage of 50 to 70 volts. However, at the area 2) between the P-well region 111 and the N- region adjacent to the gate electrode 117, the sustaining voltage i attenuated by the electric field of the aluminum lead line 119. More specifically, holes or minority carriers in the N- region are attracted towards the surface of the semiconductor substrate by the electric field of the aluminum lead line 119 which is disposed above the low concentration impurity diffused region (N- region) of the drain in the N-channel MOSFET. As a result, the surface density of carriers in the N- region is varied, causing, at a particular initial concentration rate, the surface area of the N- region to be inverted into a P-type of semiconductor by the action of the electric field of the aluminum lead line 119. The inverted P-type region is then approximated to the high concentration impurity diffused region (N+ region) so that electric field lines can be converged at the substrate surface. Accordingly the sustaining voltage at the PN junction will be decreased. This phenomenon is emphasized when the low concentration impurity diffused region of the drain is decreased in the impurity concentration for the purpose of increasing the drain junction sustaining voltage. Also, at the junction area 3) between the P-well region 111 and the far N- region from the gate electrode 117, the concentration of carriers at the surface of the N- region is varied by the electric field of the aluminum lead line 119 arranged above the N-region. But, unlike the PN junction area 2), the junction area 3) is rarely affected by the electric field of the gate electrode 117 and its sustaining voltage will be less attenuated than that of the area 2).
FIG. 5 is a characteristic diagram showing the change of the sustaining voltage of the drain junction in relation to the potential of the aluminum lead line 119 arranged above the drain region. When the aluminum lead line 119 is identical to the potential of high level to the drain region and a difference in the supply voltage between the higher and lower levels is more than 48 volts, the supply current will sharply increase. Also, when the aluminum lead line 119 is low in potential as well as the gate electrode 117, the supply current will sharply be increased by more than 43 volts of the supply voltage difference between the higher and lower levels. As apparent from the characteristic diagram of FIG. 5, the junction sustaining voltage will drop about 10% from 48V to 43V corresponding to a decrease in the potential of the aluminum lead line 119.
The change of the junction sustaining voltage with the potential of the aluminum lead line 119 disposed above the drain area indicates that a plurality of different drain sustaining voltages exist in the same channel MOSFET depending on the peripheral conditions. In other words, the sustaining voltage or leak current is varied by the content of a signal and the assessment of the sustaining voltage in an integrated circuit will be troublesome.